For lovers of digital technology, a frequency multiplying device may be of interest, the output of which has a number of pulses that is a certain integer number of times greater than the number supplied to the input. A diagram of such a device is shown in the figure.
Input pulses U„ are supplied to the driver, made on the DD1 chip. Regardless of the duration of the input pulses, short high-level pulses are generated at the non-inverting output (pin 6 of the DD1 microcircuit), the duration of which is determined by the parameters of elements C1, R1 and the built-in resistance of the microcircuit (about 2 kOhm). Their repetition period corresponds to the period of the input pulses.
The generated short pulses arrive at two inputs (pins 2 and 3) of the counter, made on the DD2 chip, and reset it to zero. At the four outputs of the counter (FO - F3) the level is set to log.0, and at the output of the element DD3.3 - the level is log. 1 regardless of the position of switch SA1. Log.1 level at one of the inputs of element DD3.4 (the duration of this level coincides with the duration of the period of input pulses) allows the passage of a series of pulses through the second input from the generator on elements DD3.1 and DD3.2. From the output of element DD3.4, pulses are supplied to the counting input of microcircuit D02 (pin 14). The output pulses will stop when the logic 1 level is applied to the input of element DD3.3. This depends on the position of switch SA1. In position 1 ("x2"), the log.1 level appears after two pulses pass through the counting input, i.e. the device multiplies the input pulses twice, in position 2 ("x4") - four times, and in position 3 ( "x8") - eight times.
For proper operation of the device, it is necessary to fulfill the requirement that the frequency of its own generator is at least 10 times higher than the frequency of the input pulses. At nominal
the values of the capacitors and resistors shown in the diagram, the frequency of the generator is 100 kHz, and therefore the frequency of the input pulses should not exceed 10 kHz. Due to the delay of the edges of the input pulses during operation of the DD1 microcircuit, there is a slight delay in the output pulses compared to the input ones. The delay can be reduced by reducing the resistance of resistor R1, but its resistance cannot be reduced to less than 1 kOhm.
Editor's note.
The device can use domestic radio signals K155AG1 (DD1), K155IE2 (DD2), K155LAZ (DD3), KD521A (VD1 and VD2).
Primary source: Honesty multiplier. "Hobi-electronics 1",
collection - Sofia, "ECOPROGRESS", 1992
Source: RADIO N9, 1997
| This diagram is also often viewed: |
Doubler on a compound stage. The device (Fig. 14.18) is assembled using two transistors of different conductivities. In the initial state, both transistors are closed. The input is a harmonic signal. Positive polarity of the input signal turns on the transistor VT1 and turns off the transistor VT2. Flowing transistor current VT1 creates a voltage drop across the resistors R3 And R4. The first output will have a signal in phase with the input signal, and the second output will have a signal out of phase. If the resistances of the resistors are equal R3 And R4 the amplitudes of these signals will be equal. The negative half-wave of the input signal will close the transistor VT1 and opens the transistor VT2. On Exit 1 a signal will appear that is out of phase with the input signal, and Exit 2- will be in phase with the input signal. Thus, when a sinusoidal signal is applied to the input, Exit 1 all half-waves will be positive, and Exit 2- negative. The doubler operates in the frequency range from 200 Hz to 20 kHz.
Rice. 14.18 Fig. 14.19
Transistor doubler. The doubler (Fig. 14.19) consists of two transistors. The first transistor operates in a circuit with a collector-emitter load, and its transmission coefficient is equal to unity. The second transistor operates in a circuit with OB. The input signal creates at the emitter VT2 current that is at the collector load R3 creates a voltage equal in amplitude to the input voltage. Thus, the positive half-wave of the harmonic signal passes through the transistor VT1And allocated to the resistor R3with phase shift of 180°, and the negative half-wave passes through the transistor VT2 without phase change. As a result, the voltage across the resistor R3 will have the form obtained after full-wave rectification of the input signal. The doubler operates over a wide frequency range, which is determined by the type of transistors used.
Transistor multiplier. The frequency doubling circuit for the input harmonic signal (Fig. 14.20) consists of two stages. Each stage increases the signal frequency by 2 times. A positive half-wave of the input signal with an amplitude of 0.5 V opens the transistor VT2. The negative half-wave passes through the transistor VT1. These two signals are summed across a resistor R2. Transistor VT2 inverts the input signal,a VT1- does not invert. On a resistor R2 a full-wave rectification signal is generated. This signal is fed through an emitter follower to the second stage. The amplitude of the repeater output signal is 0.6 V.
Rice. 14.20 Fig. 14.21
Diode multiplier. The input harmonic voltage (Fig. 14.21) is supplied to the transformer. The secondary winding of the transformer includes two phase-shifting chains. In them, the phase of the harmonic signal shifts by 120°. As a result, phase-shifted signals pass through the diodes. At the input resistance of the transistor they are summed. The third harmonic of the total pulsating signal is isolated by the circuit. The ratings of the elements of phase-shifting chains are designed for a frequency of 400 Hz.
Rice. 14.22
Detector frequency doubler. This doubler (Fig. 14.23) is based on full-wave rectification using two transistors VT1 And VT2. The negative half-wave of the op-amp's output voltage passes through the transistor VT1, and positive - through a transistor VT2. Resistors R6 And R8 are chosen to be the same, so the transmission coefficients of both half-waves are equal. To eliminate distortions in the output signal shape caused by the influence of the threshold initial section of the transistor characteristics, an op-amp with nonlinear feedback is used. With potentiometer R2 the op-amp output is set to a voltage corresponding to minimal distortion of the output signal. The doubler works well with a triangular input signal. Up to ten multiplier circuits can be connected in series for this input waveform.
Rice. 14.23 Fig. 14.24
Rice. 14.25
Differential doubler. The frequency doubler (Fig. 14.24) consists of an emitter follower assembled on a transistor VT1, and an amplifier stage built on a transistor VT2. The input signal through capacitor C1 enters the base of the transistor VT1. At the emitter, this signal is added to the signal that passes through the transistor VT2. Transistor VT2 operates in nonlinear mode. It passes the negative half-waves of the input signal. The phase-inverted input signal will be subtracted from the emitter follower signal. The level of interacting signals can be adjusted using resistors R4 And R5. Resistor R4 controls the amplitude of the negative half-wave, and the resistor R5 regulates the ratio of the emitter signal to the collector signal.
Square wave frequency doubler. Device (Fig. 14.25, A) converts a harmonic input signal into a square wave signal with double frequency. The input signal enters the emitters of the transistors VT1 And VT2. Transistor VT1 operates in limited mode. The second transistor also limits the signal, but due to capacitor C1, the output signal shifts by 90° relative to the input. Two limited signals are summed through resistors R6 And R7. Total bipolar signal using transistors VT3 And VT4 converted to a double frequency signal. Signal diagrams at various points are shown in Fig. 14.25, b. The doubler operates over a wide frequency range from 20 Hz to 100 kHz. This range can be covered by using the appropriate capacitance of capacitor C1. The input signal must have an amplitude of at least 2 V.
Compensation multiplier. The compensation type frequency multiplier (Fig. 14.26) is built on a single transistor. The amplitude-limited signal is summed with a harmonic input signal across a resistor R1 In Deevlta, a signal is generated at the output, the frequency of which is 3 times higher than the frequency of the input signal. The output waveform is not perfectly harmonic. This signal must be passed through a filter to reduce the level of high harmonics. The waveform is greatly influenced by the clipping level of the transistor. At small cutoff angles of the output signal, high-frequency spectral components are significantly reduced. At the same time, the amplitude of the third harmonic decreases.
Rice. 14.26 Fig. 14.27
Op-amp divider. Divider (Fig. 14.27, A) built on the quadrant distribution of the total signal at the output of the op-amp. On Input 1 a local oscillator signal with an amplitude of 0.1 V is generated, Input 2 - converted signal. The dependence of the amplitude of the output signal on the converted signal is shown in Fig. 14.27, b.
Frequency multipliers are an externally excited oscillator whose oscillatory circuit is tuned to a frequency that is a multiple of the input signal frequency. Since the input signal is harmonic, to enrich its spectrum it undergoes nonlinear transformations (section 2.7.). When choosing a rest point on the current-voltage characteristic at the origin or to the left of the origin, a sequence of current pulses occurs, as shown in Fig. 3.8.
Rice. 3.8. An approximate view of a sequence of current pulses through a nonlinear element
Half of the phase angle within which current flows through a nonlinear element is called the cutoff angle. So, in Fig. 3.8 – cutoff angle, which depends both on the position of the resting point P and on the amplitude of the input signal. As the amplitude of the input signal increases, a dip may appear in the current pulses. When transistors and electronic amplifier tubes are used as nonlinear elements, the failure is caused by the appearance of a reverse current at large amplitudes of the input signal (see laboratory work “Study of an externally excited oscillator”).
Spectrum of a sequence of current pulses through a nonlinear element
has harmonic amplitudes that decrease with the number of harmonics. The direct component of the current I 0 and the amplitude of the harmonics depend on the cutoff angle and can be calculated through the Berg coefficients (A.I. Berg - Soviet radio physicist, academician of the USSR Academy of Sciences):
; ; ;…, (3.10)
where I m and – pulse amplitude (maximum pulse value);
, , , …, – Berg coefficients, depending on the cutoff angle and calculated using the following formulas:
; (3.11)
where n = 1, 2, 3,…
In Fig. 3.9 shows Berg's graphs.
Rice. 3.9. Berg charts
When the circuit isolates the nth harmonic, the power of the isolated oscillations P k and the efficiency of the generator are calculated using the following formulas:
, (3.14)
where E K is the voltage of the power source (for example, collector voltage);
P I – power consumed by the power source;
– power source voltage utilization factor.
When the frequency is multiplied, the electrical energy supplied to the oscillatory circuit in the braking phase (see the principles of generating electromagnetic oscillations) of the first period of oscillation (Fig. 3.10) maintains a constant value of the signal amplitude during the period of time when this energy is supplied. Then the amplitude decreases exponentially:
where , r is the circuit resistance, taking into account energy losses in the circuit, L is the inductance of the oscillatory circuit.
Rice. 3.10: A– approximate type of voltage on the circuit (at the generator output) in frequency multiplication mode n=2; the dotted line shows the dependence of the damping of free oscillations; b– current pulses of an active nonlinear element (for example, a transistor), the square of the area of which is proportional to the electrical energy entering the circuit through the period of natural oscillations; impulses arrive in the inhibitory voltage phase
Obviously, the smaller the value of , the more stable in amplitude the oscillations at the output of the frequency multiplier will be. Energy losses in the circuit are taken into account by the quality factor of the circuit
Where 
– energy stored in the circuit;
– energy loss in the circuit during the oscillation period;
.
The integral is taken in parts:
Where 
;
Substituting into (3.16) and the loss energy E sweat, and taking into account that the quality factor Q of the circuit is determined at the resonant frequency 
, we finally get
where is the characteristic impedance of the circuit.
The expression for the characteristic impedance of the circuit can be derived from the equality of the energies stored in the magnetic field of the coil and the electric field of the capacitor:
. Where 
, .
The quality factor of the loaded circuit Q N, that is, calculated by definition (114), when the output of the generator with external excitation is connected to the load, is equal to:
Q Н = 150…200, (3.18)
and the characteristic impedance of the circuit
50…200 (3.19)
depending on the radio frequency range.
With a high quality factor Q H, that is, very small losses of electrical energy during one oscillation period, the amplitude of damped oscillations over the time interval t changes insignificantly; and this factor, which affects the amplitude stability of the frequency multiplier, can be neglected.
Another significant factor affecting the stability of the oscillation amplitude from the output of the frequency multiplier is the cutoff angle. Since current pulses supply energy to the oscillatory circuit, their duration should not exceed T/2, where T is the period of oscillation in the circuit (see Fig. 3.10). Only in this case, all the energy entering the circuit falls on the braking phase of the voltage (electric field) and the kinetic energy of charge carriers in active nonlinear elements turns into electrical energy of oscillations in the circuit. Therefore, as the frequency multiplication factor of the input signal increases, the cutoff angle should decrease. A decrease will lead to a decrease in the amplitude of the current pulse I m and, and this, in turn, will lead to a decrease in the harmonic amplitude at the output of the frequency multiplier (3.10). If the cutoff angle is not changed, then the current pulses will have a duration 
. This will lead to significant amplitude instability of oscillations, since energy will be supplied to the circuit not only in the braking phase, but also in the accelerating phase of oscillations. It is easy to verify experimentally that when oscillations in the circuit are disrupted (laboratory work: “Study of a generator with external excitation”).
A two-stage input signal frequency multiplier circuit is shown in Fig. 3.11. The first stage is assembled on transistor VT1, and the second on transistor VT2. Resistors R b provide closure of the circuit for the flow of base current I b and create negative biases at the bases of their transistors due to the constant component of the base current I b0.
Rice. 3.11. Two-stage frequency multiplier circuit
Example: to ensure a certain cutoff angle, it is necessary to shift the rest point P to the left from the origin (see Fig. 3.8) by 0.2 V. Base current pulses i b (t) should be written in the form (3.9), where . Then R b = U be0 /I b0 = 0.2/I b0. At I b0 = 30 µA, R b = 6.8 kOhm.
An amplifier assembled on transistor VT2 is designed to amplify harmonics with frequency f 0 = m f AG to the level of normal operation of the second multiplication stage. The amplifier must operate in linear mode. It is assembled according to a circuit with a fixed voltage at the base and emitter stabilization (see calculation of this amplifier).
Resistor R e ensures temperature stabilization of the resting point. Capacitor C e eliminates negative feedback (NFB) on alternating voltage; To do this, the following condition must be met: X se<< R э.
Resistors R k provide the calculated voltage values between the collector and emitter U k of transistors.
Filter capacitances C f1 and C f2 are selected from the condition of cascade decoupling at compositional frequencies close to the resonant frequencies of the oscillatory circuits f 01 and f 02 .
As already noted, to increase the frequency multiplying factor in one cascade, it is necessary to reduce the cutoff angle, which leads to a decrease in the amplitude of the pulses I m and, consequently, the amplitude of the multiple frequency harmonics released by the circuit, and this, in turn, limits the multiplying factor. To increase the frequency multiplication factor in one stage, it is necessary to include two additional devices in it: a limiter and a linear resistive amplifier, as shown in Fig. 3.12.
Rice. 3.12. Frequency multiplier stage, including a limiter on transistor VT1, a linear amplifier on transistor VT2, and a generator with external excitation on transistor VT3
The resistive amplifier assembled on VT2 is an amplifier with a fixed base current, a detailed calculation of which is given in the next section. This amplifier increases the pulse amplitude without changing the cutoff angle, which is set by choosing the resting point P of the limiter assembled on VT1. The position of the rest point on the input characteristic of transistor VT1 is determined by calculating the resistor R b1. Trimmer resistor R b2 allows you to set the critical operating mode of the generator with external excitation (see Generator with external excitation).
Frequency multiplication This is the process of producing vibrations with a frequency that is a multiple of the frequency of the original vibration.
Frequency multiplication is used if for some reason it is impossible to obtain an oscillation with the required frequency (at frequencies of several hundred megahertz and higher) or if it is necessary to obtain an oscillation frequency with an accuracy of a multiple of a certain frequency.
Frequency multiplication can be accomplished by three methods:
Cutoff angle method
This method is used to obtain a harmonic vibration with a multiple of the frequency from another harmonic vibration. To obtain an oscillation with the required frequency, it is necessary to transform the spectrum of the input signal (introduce new harmonic components into the spectrum). To transform the spectrum, a nonlinear element operating in cutoff mode is used. To do this, the position of the operating point is set, using the bias voltage U 0, outside the current-voltage characteristic of the element (Figure 26). In this case, the element opens only at the moment when the voltage of the input signal Uin reaches a certain initial value Un. When Uin
Figure 26 - To explain the operating mode of a nonlinear element when multiplying frequency
The cutoff angle can be determined from the expression
cos ? = (Un— U 0 )/ Um (36)
where Um is the amplitude of the input oscillation.
The amplitude of the output current pulses is determined by the expression
Im = SWed? Um(1 — cos q) (37)
The spectrum of the resulting periodic sequence contains many components located at frequencies that are multiples of the input signal frequency. The amplitude of these components is determined by the expression
I'm k= ak(q) ? Im (38)
where Im k is the amplitude of the k-th component of the response spectrum;
a k (q) is the proportionality coefficient for the kth spectrum component;
Im is the amplitude of the output current pulses.
The coefficients a k (q) depend on the cutoff angle and are determined by Berg functions. Graphs of Berg functions for the constant component and the first three harmonics are presented in Figure 27.
Figure 27 - Graphs of Berg functions
To determine the coefficients, it is necessary to determine the values of a k for all functions at the required cutoff angle q. For example, it is necessary to determine the proportionality coefficients for q=80°. Using the graph a 0 we determine the proportionality coefficient for the constant component at a value of q=80°. It is equal to a 0 (80°)"0.28. Similarly, we determine the value of the coefficients a 1 (80°)"0.47 (by function a 1), a 2 (80°)"0.24 (by function a 2)? a 3 (80°)»0.05 (by function a 3).
When multiplying the frequency, it is necessary to obtain an oscillation with the required frequency of the greatest possible amplitude. This is possible at maximum values of a k (q). In turn, the maximum of a k (q) is observed at the maximum points of the corresponding Berg functions. Each function has a maximum at one specific cutoff angle. The cutoff angle at which the greatest amplitude of the required harmonic is observed is called optimal cut-off angle. So the optimal cutoff angle for the second harmonic is q=60°, and for the third q=40°. The optimal cutoff angle is set by the bias voltage U 0 .
This method allows you to obtain vibrations with a multiplicity of 2 and 3. This is explained by the fact that the amplitudes of the harmonic components in the response spectrum with large numbers have too small an amplitude. Setting the required optimal cutoff angle for these components will lead to a decrease in the amplitude of the output current pulses and again to the production of oscillations with a very small amplitude.
The schematic diagram of a frequency multiplier implementing the cutoff angle method is shown in Figure 28.
Figure 28 - Schematic diagram of a frequency multiplier on a transistor
This multiplier uses bipolar transistor VT1 as a nonlinear element, operating in the collector current cutoff mode. The transistor is supplied with supply voltage Ek and bias voltage U0. The input voltage is supplied through the oscillating circuit L1 C1. An oscillatory circuit is used to obtain greater stability of the input oscillation frequency, i.e., so that the transistor input receives an oscillation containing only one harmonic at the required frequency, and thereby eliminates distortion of the resulting oscillation. The transistor transforms the vibration spectrum. Then the harmonic with the required frequency is isolated by the oscillating circuit L2 C2, used as a bandpass filter.
The characteristic of the frequency multiplier is multiplication factor, showing how many times the frequency of the output oscillation exceeds the frequency of the input oscillation
Ku=fout/fin(39)
As noted above, the multiplication factor of this multiplier does not exceed 3. To obtain Ku>3, it is necessary to use multistage multiplier circuits (serial connection of several multipliers). For example, to obtain Ku=6, it is necessary to connect two multipliers with Ku=2 and Ku=3 in series.
Frequency multiplication methods using PPI and radio pulse
Method for obtaining multiple frequencies using PPI is based on the fact that the spectrum of a periodic sequence already contains harmonic components at multiple signal frequencies, i.e., multiples of the first harmonic (Figure 29). Therefore, it is only necessary to isolate the harmonic with the required frequency from the spectrum. To obtain vibrations with a larger amplitude, it is necessary to isolate the harmonic components of the first lobe of the spectrum, and the amplitude of the components decreases less if the number of components in the lobe is greater. Thus, periodic sequences with a duty cycle greater than 14 are used to multiply the frequency.
This method allows you to increase the oscillation frequency tens of times.
Method of obtaining multiple frequencies using a radio pulse consists in multiplying the original oscillation with another high-frequency harmonic oscillation, i.e., the harmonic carrier is modulated by a pulse oscillation. In this case, the spectrum of the pulse oscillation is transferred to the frequency range of the harmonic oscillation, resulting in the formation of a radio pulse. Then, a harmonic with the required frequency is isolated from the spectrum of the received radio pulse. This method allows you to obtain an oscillation with a frequency hundreds of times higher than the frequency of the original oscillation.
Figure 29 - Frequency multiplication using PPI: a) original PPI with frequency fs and duty cycle 17; b) SPI spectrum; c) the resulting oscillation with a frequency of 10fs
SEMICONDUCTOR FREQUENCY MULTIPLIERS
Communication, communication, radio electronics and digital devices
SEMICONDUCTOR FREQUENCY MULTIPLIERS 17. Transistor frequency multiplier 17. Diode frequency multipliers 17. Purpose operating principle and main parameters Frequency multipliers in the block diagram of the radio transmitter, see.
Lecture 1 7 . SEMICONDUCTOR FREQUENCY MULTIPLIERS
1 7 .2. Transistor frequency multiplier
1 7 . 4 . Control questions
17.1. Purpose, principle of operation and main parameters
Frequency multipliers in the block diagram of a radio transmitter (see Fig. 2.1) are located in front of the power amplifiers of RF or microwave oscillations, increasing the frequency of the exciter signal by the required number of times. Frequency multipliers can also be part of the exciter or frequency synthesizer itself. For the input and output signal of the frequency multiplier we write:
(17.1)
where n frequency multiplication factor by an integer number of times.
Classification of frequency multipliers is possible according to two main criteria: the principle of operation, or the method of implementing the function (17.1), and the type of nonlinear element. According to the principle of operation, multipliers are divided into two types: based on synchronization of the oscillator frequency with an external signal (see Section 10.3), in P times lower in frequency (Fig. 17.1, a), and using a nonlinear element that distorts the input sinusoidal signal, and isolating the required harmonic from the resulting multi-frequency spectrum (Fig. 17.1, b).
Rice. 17.1. Frequency multipliers.
Based on the type of nonlinear element used, frequency multipliers of the second type are divided into transistor and diode.
The main parameters of the frequency multiplier are: frequency multiplication factor n ; output power nth harmonic Р n, 1st harmonic input power R 1, conversion factor K pr = P n / P 1 ; efficiency = Р n / Р 0 (in the case of a transistor multiplier), the level of suppression of spurious components.
Lack of frequency multipliers (Fig. 17.1, A ) The first type consists in narrowing the synchronization band with increasing harmonic number P. For frequency multipliers of the second type, the conversion coefficient decreases To pr with increasing p. Therefore, they are usually limited to the value n = 2 or 3 and, if necessary, turn on several frequency multipliers in series, alternating them with amplifiers.
17.2. Transistor frequency multiplier
The circuit of a transistor frequency multiplier (Fig. 17.2) and the method of calculating it are practically no different from an amplifier.
It is only necessary to configure the generator output circuit to n th harmonic and select the cutoff angle value =120 / n , corresponding to the maximum value of the coefficient n ( ). When calculating the output circuit, the expansion coefficient of the cosine pulse in the 1st harmonic 1 ( ) should be replaced by the coefficient for nth harmonic n ( ). A circuit in the output circuit tuned in resonance with n - and signal harmonics, must have satisfactory filtering properties.
Rice. 17.2. Transistor frequency multiplier circuit.
The multiplication factor of the circuit in Fig. 17.2 usually does not exceed 34 times with an efficiency of 1020%.
17.3. Diode frequency multipliers
The operation of diode frequency multipliers is based on the use of the nonlinear capacitance effect. The latter uses a reverse-biased barrier capacitance p - n -transition. Semiconductor diodes specifically designed for frequency multiplication are called varactors. At =0.5 and 0 =0.5 V for the nonlinear capacitance of the varactor we obtain:
, (17.2)
where and - reverse voltage applied to p - n junction.
The graph of the nonlinear function (17.2) is shown in Fig. 17.3.
Rice. 17.3. Graph of nonlinear function (17.2).
The charge accumulated by a nonlinear capacitance is related to voltage and current by the following dependencies:
, (17.3)
Two main circuits of diode frequency multipliers with varactors are shown in Fig. 17.4.
In the parallel diode multiplier circuit (Fig. 17.4, A ) there are two circuits (or filters) of a series type, tuned in resonance accordingly with the frequency of the input and output n signals. Such circuits have low resistance at the resonant frequency and high resistance at all others (Fig. 17.5).
Rice. 17.5. Dependence of circuit resistance on frequency.
Therefore, the first circuit, tuned to resonance with the input signal frequency o, passes only the 1st harmonic of the current, and the second circuit, tuned to resonance with the output signal frequency n , - only n th harmonic. As a result, the current flowing through the varactor has the form:
, (17.4)
Since the varactor capacitance (17.2) is a nonlinear function, then according to (17.3) at current (17.4) the voltage on the varactor is different from the sinusoidal shape and contains harmonics.
One of these harmonics, to which the second circuit is tuned, passes into the load.
Thus, with the help of a nonlinear capacitance, the device converts signal power with frequency into a signal with frequency n , i.e. frequency multiplication.
The second sequential frequency multiplier circuit works in a similar way (Fig. 17.4, b), in which there are two circuits (or filters) of parallel type, tuned into resonance according to the frequency of the input and output n signals. Such circuits have high resistance at the resonant frequency and low resistance at all others. Therefore, the voltage on the primary circuit, tuned in resonance with the frequency of the input signal , contains only the 1st harmonic, and on the second circuit, tuned to resonance with the frequency of the output signal n , - only n th harmonic. As a result, the voltage applied to the varactor has the form:
, (17.5)
where U 0 - constant bias voltage on the varactor.
Since the varactor capacitance (17.2) is a nonlinear function, then according to (17.3) at voltage (17.5) the current flowing through the varactor is different from the sinusoidal shape and contains harmonics. One of these harmonics, to which the second circuit is tuned, passes into the load. Thus, with the help of a nonlinear capacitance in the circuit, the signal power is converted with a frequency into a signal with frequency n , i.e. frequency multiplication.
Varactor frequency multipliers in the DCV range at n =2 and 3 have a high conversion factor K pr = P n / P 1 = 0.6…0.7. For large values P in the microwave range value K pr decreases to 0.1 and below.
17.4. Control questions
1. How is the frequency of oscillations multiplied?
2. Draw a circuit of a transistor frequency multiplier.
3. Explain why it is possible to multiply the oscillation frequency using a nonlinear capacitance.
4. Draw circuits of diode frequency multiplier of series and parallel type. What are the differences between them?
